Thermal Modeling and Management in Ultrathin Chip Stack Technology

—This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.


I. INTRODUCTION
R ECENT development of advanced packaging technolo- gies such as three-dimensional (3-D) stacking, multichip modules (MCMs) and 3-D stacks of MCMs provided an opportunity for significant reduction in system mass, volume and power consumption [1]- [5].During the last 30 years, the thickness of packages have been divided by ten.The advancement of thinning, transport and attachment technology and the modification of existing planarization and interconnection techniques  has led to the use of Ultra Thin Chip Stacking (UTCS) technology [6].This new integration technique we have studied can be described as follow (Fig. 1): chips are thinned down to 10 m [7] and then, using planarization techniques as used in semiconductor processing, the 3-D stack is realized on a silicon substrate by depositing layers of BenzoCycloButene (BCB) onto which a metallization pattern is formed.The thinned chips are placed on top of each dielectric layer and the vertical interconnection is achieved with metallized vias.The final stack has a thickness comparable to the standard silicon chips one.For this proposed technology, besides the imperatives dictated by the whole of the developed fabrication sequence and the induced residual thermomechanical stresses, characteristics of any heterogeneous assembly [8], the possible limitations by thermal dissipation effects can influence a lot on the design rules definition.Indeed, on the one hand, the vertical integration principle itself is an obvious factor of heat sources concentration, and on the other hand the use of BCB having a poor thermal conductivity, as adhesive and planarization layer, degrades the heat extraction efficiency through the vertical path.
This paper is precisely focused on the analysis of thermal behaviors for this novel compact integration technology by approaching the four following points: 1) the modeling of single-level structures and the study of a possible limitation by the low thermal conductivity of BCB layers; 2) a first characterization of a single level structure by the study of the transient thermal response; 3) a suggestion for the optimization of conductive thermal path in multilevel structures; 4) the thermal evaluation of our first demonstrator based on a three-levels stacking structure for space application.This modeling approach, which one wishes as rigorous as possible, is based on 3-D FEM calculations.Analytical 1-D projections will come to support the analysis when that can be justified.

II. MODELING OF SINGLE-LEVEL STRUCTURES AND CHARACTERIZATION OF SPECIFIC BEHAVIORS
The first modelization phase considers a single level structure which is defined on Fig. 2, in conformity with the UTCS technique specifications and the typical design rules of MCM-D technology.Essentially, the width and thickness of the copper interconnection lines are 20 and 2 m respectively; the 8 m high copper stud is assumed parallelipedic (30 m 30 m); this simplifying assumption to traduce the real structure allows to simplify the FEM model meshing and does not influence the definition of the conductive thermal path.The thickness of the thinned die is 10 m and the PTCB specific device considered is a multi-purpose test chip designed for experimental characterization of the thermal, electrical and reliability performance of chip packaging and interconnection technologies (current chip-on-board and flip-chip techniques more particularly) [9].The lay-out of the 5 5 mm unit cell illustrated on Fig. 3 includes two heating resistor areas (3900 1850 m ) symmetrically placed around the center of the chip and three diodes are used for temperature sensing.
The 3-D FEM thermal model was built with ABAQUS software [10].The boundary conditions are on the one hand the fixed reference temperature-chosen to 0 C-at the back side of the stacked structure, and on the other hand the adiabatic behavior for the top and lateral faces.Due to the uncertainties on the thermal conductivities of BCB and electroplated copper, and especially their variations with temperature, it was considered, for this first modeling phase, a linear thermal behavior by using the thermal conductance values reported in Table I.The other physical data also in this table will be used in the analysis presented in the following sections.We can note that the 0.18 W/m.K value retained for the BCB material is the pessimistic thermal conductance value given by the supplier (0.18 to 0.24 W/m.K range [11]).A characterization by thermoreflectance, at the micrometric scale [12] and on our  specific samples, confirms this data and permits to verify also that the thermal transfer at the BCB/Si or BCB/Cu interfaces does not induce a significant limitation compared to the thermal resistance of the BCB adhesive layer with our technological species [13].Fig. 4 shows the results obtained for a slice of the first level PTCB/carrier substrate that contains a single pad and its connection via a copper stud.It is clear that the thermal conduction occurs mainly through the thinned active PTCB chip, and that the essential part of the thermal resistance is defined by the conduction into the 3 m thick BCB adhesive layer.An equivalent lumped thermal model established from a 1D conduction approach in all constitutive regions of the stacked structure with  their connections allows an obvious interpretation of these observations.
A presentation of the simulated results now relative to the complete PTCB single-level structure previously described is given in the Fig. 5.As expected, the natural 3-D thermal conduction induces a temperature variation overall the surface of the heat resistor, and most particularly on the periphery.Here, for the particular use of the PTCB test device-which is the thermal characterization of the first stacked thin layers and not the layers of lower rank, as usual in the characterization of the packaging techniques-the temperature deviation between the hotter region and the diode sensor will not be neglected.
Apart the data necessary to the verification and the characterization of the single level test structure, these first modeling results (Fig. 5) give also a first evaluation of the heat transfer capabilities in UTCS technology.The obtained results show a value of the maximum temperature that leads to an apparent thermal resistance of 2.74 C/W that can be compared to the 2.31 C/W and 2.77 C/W values calculated by considering a 1D thermal conduction through only BCB or a Si (10 m)/BCB (3 m)/Si (500 m) tri-layers structure, respectively.If we consider uniform heat sources of great dimensions it appears that the limitation of the thermal transfer through a 3 m adhesive BCB layer leads to an heating of five times higher than the one of the structure on its unthinned source substrate (500 m thick).
The possibility to integrate, with this new technology, active devices with dissipating zones very confined thus presenting reduced areas has been investigated.Here, the most affirmed 3-D character of the thermal conduction, with more particularly the influence of heat flux spreading in the Si thinned die with a very high conductivity compared to BCB (Fig. 6), leads to a saturation of the thermal resistance when the heat source area decreases as shown in Fig. 7.The simulation results show for an active area of 10 10 m an increase of the apparent thermal resistance compared to the unthinned device one with only a factor 2.4.However, the high related values obtained have to be considered with caution for the UTCS applications, because they'll fix the maximum temperatures that have to remain lower than the temperature allowable for functional and reliability limits.For the design rules optimization, we have calculated sensitivities to BCB adhesive layer and Si thinned die thicknesses, calculated as a function of the heat source area.
The results illustrated on Fig. 7(a) and (b) show that i) a reduction of BCB thickness gives an improvement with the same amplitude only for great areas, the domain where the thermal conduction has a quasi-1-D behavior; ii) at the opposite, a die thinning limited to 15 m rather than 10 m (variation is 33% relative to 15 m value) allows to benefit from the effects of heat spreading in the case of heat sources with small areas.A 24% decrease is calculated for thermal resistance in the saturated region where the effective dissipating section is quasifixed by the heat spreading mechanism.

III. TRANSIENT THERMAL CHARACTERIZATION
Transient temperature measurement is the most suitable method for experimental characterization of packaging techniques [14], [15].Indeed, the deduced thermal impedance function can be interpreted as a cross sectional view of the internal package heat flow structure that allows to well identify the different resistant components in the complete thermal path.This is all the more interesting as the matter is to well characterize the possible intrinsic thermal limitation in our new stacking technology.
As previously mentioned, the measured temperatures in the considered PTCB experimental test chip by means of diode sensors are underestimation values with respect to the actual temperature in the active heat resistor.This discrepancy can be important, in relative value, since the analysis of the thermal impedance is focused on the first phases of the thermal transfer, and can be an error source in the extraction of the relevant physical properties.To take into account this significant thermal decoupling between the heat resistor and the thermal sensor, it is therefore necessary to perform a true 3-D numerical simulation.Our FEM thermal modeling approach of the experimental set-up satisfies this requirement.
Transient experiments have been performed with a stacked structure mounted on DIL package.In the study the PTCB chip thinned down to 20 m is glued to the carrier with a 3 m BCB layer; the 600 m thick silicon host substrate is attached on the alumina header of the package (760 m thick) by means of the epoxy (50 m).Measurements are performed in the environment of the laboratory with still air.One or two heating resistors of the test structure are activated under 2 W power each.This transient thermal characterization shows a significant limitation by BCB/Si interfacial conductances; the extracted value-1.3 10 W/m .K-defines an equivalent resistance which is in the order of four times higher than the one of the 3 m thick BCB layer.A first estimation on one different study sample, under steady-state and on wafer probe station predicts only a 50% increase (the estimation gives an extracted interfacial thermal conductance value equal or greater than 3.5 10 W/m .K).Regarding this erratic behavior, one explanation may be found in the presence of sticking defects and their erratic localization related to temperature diode sensor.As a matter of fact, it is the transverse thermal transfer length in the thinned device which defines the sensitive area to the possible sticking defects.So, one device having only little and few defects near the diode sensor gives an apparent thermal resistance greater than the one with bigger defects but more distant of sensor.

IV. HEAT EXTRACTION OPTIMIZATION BY INTERLEVEL THERMAL DRAINS
Considering the results already obtained for the analysis of the thermal behavior in the one level structure, we have begun the study of the two levels stacking by considering directly the evaluation of the heat extraction by means of copper grid or full metal plate below the second level thinned chip, as is schematized in Fig. 9.For all the analysis made, we have considered the following parameters for the stacking: 1) Si carrier is 500 m thick; 2) the thicknesses of the first and second thinned Si chips are 10 m;  3) thickness of the first adhesive BCB layer is 3 m; 4) thickness of the second BCB layer for planarization of first level is varied from 3 to 15 m; 5) the width and spacing couple of the copper grid are varied from the W: 10 m/S: 30 m to 20/60 m; 6) the thickness of the copper grid or the copper plate is considered in the 2-10 m range; 7) finally, the third BCB layer for the adhesive of the second level chip is fixed to 1 m.In this first modeling step, the edges of either copper grid or copper plate are assumed to be at the reference temperature (the same as the host substrate temperature).Indeed, in this proposed new stack technology, the lateral heat extraction at the periphery of the structure will be ensured through copper via networks whose dimensions will be here much more favorable for the transfer if one considers the cross section and length of thermal path.It is thus allowed to neglect this contribution at this stage of the evaluation.Considering the double symmetry, into the plane, of two stacked PTCB, we have limited the 3-D numerical calculation to the quarter of the structure (Fig. 10).The surfacic density of dissipated power into the one, the other or both levels was considered at 14 W/cm that corresponds to a power of 1 W into one thermal resistor.
Fig. 11(a) and (b) show the obtained isotherms onto the surface of the second level and onto the upper side of the copper grid for m, m and m, for a single thermal excitation in the second level (called Heat ).Fig. 11(c) compares the temperature plots on the axis of symmetry , for each one of the surfaces of the Si thinned chips located at the level 1 and 2, and for three thermal excitations heat , heat and heat .As expected for this study of the linear regime, the principle of superposition is verified and this is an interesting validation of our numerical results.Finally, still in the frame of the 3-D simulation of two stacked PTCB structures, Fig. 12 compares the behaviors for a copper grid, a full  plate and the case where the metal was suppressed and replaced by a BCB layer of equivalent thickness (2 m).These results induce two comments: firstly, in the center of the structure (corresponding to the heat resistance section) the substitution of BCB mater by metal with better thermal conductivity improves obviously the vertical thermal path; secondly, the lateral heat extraction by means of copper grid or full copper plate is only effective on the structure periphery, over a relevant distance L that we define as "effective transverse thermal transfer length."To precise this behavior, particularly from a study of sensitivity to the different technological parameters, the 3-D calculation-which is too heavy-has been limited to only one slice.By another way the thermal dissipation is now considered uniform.Indeed, for our objective that is the evaluation of the lateral heat extraction capabilities, this simplification avoids the 3-D effects related to the delimitation of the heat source in comparison with the whole structure of the stacking.As an illustration of the obtained simulation results, for a copper grid having 20, 60, and 2 m for width, spacing mesh and metal thickness respectively, the temperature plots all along the structure and for each stacking level reported on the Fig. 13 show the measurement of .This distance is evaluated starting from the asymptotic variation of the temperature at the edge of the stacked structure.For the illustrated case, is around 300 m and this model predicts a value of 1 mm when the couple 15 m of BCB and 10 m of Cu is considered.Finally, Fig. 14 compares the lateral heat extraction capabilities respectively for the grid and full plate, as well as the thickness of metal plate effects mimed through thermal conductivity values.As expected, the increase of do not follow linearly the decrease of the transverse resistance component of the heat spreader.One can easily interpret this behavior by means of a "Transmission Line Model" based and simplified approach: the estimation of the transfer length, which permits to predict a tendency, is given by the following relationship: (1) It is clear that, for the structural parameters compatible with UTCS design rules, the effective transverse thermal transfer length will be small relatively to the usual die size.However, this technique can give an interesting improvement of the thermal path because in integrated circuits, the buffer devices dissipating most of the power are generally localized in this peripheral zone.Obviously, the efficiency and the interest of this extraction technique would be increased if BCB conductivity and/or BCB/Si interfacial thermal conductance would be highly altered with respect to expected properties.By allowing the heat flux spreading in the regions where the attachment is poor-voids or bubbles in the BCB adhesive layer essentially-they will contribute to the temperature uniformization.Fig. 15 illustrates a study of this improvement of capabilities by comparing the effects of three voids of 500 500 m , 250 250 m and 100 100 m respectively, for a copper grid and copper plate of 2 m thick embedded in a 3 m BCB adhesive layer.In agreement with the thermal transfer length value estimated previously for the corresponding technological configuration-m-we observe that the metal plate is really useful to spread heat flow and make uniform the temperature if the void size is lower than 500 m.

V. THERMAL EVALUATION OF SPACE DEMONSTRATOR
For the feasibility demonstration of this new ultra-compact chip stack technology we have retained a subsystem for space application.This first demonstrator, currently under development and described in [16], is a channelizer prototype including three cascaded ASICs having 1.5 1.5 cm size with 450 I/O each and dissipating 3.8 W at 33 MHz bus speed.
The aim of the present study is the research and the evaluation of the better packaging efficiency in terms of the higher degree of integration remaining compliant with spatial thermal specifications (range of allowed temperatures 90-110 C).The main specifications and characteristics retained for this study could be summarized as follows.
i) As schematized in the Fig. 16 UTCS structure is mounted on PGA package with AlN header and temperature case is maintained at the temperature board (70 C) with only thermal conduction based regulation; a three levels stacking involves 13 m thinned dies and 13 m adhesive BCB layers; for worst case estimation, we have considered five interfaces (BCB/Si, BCB/Cu and BCB/BCB interfaces) with their relative thermal conductance.ii) We have examined the thermal behavior of the four main alternatives stacking procedures illustrated on the Fig. 17: Stacking with a precise overlapping of three dies on three levels (stack ), and stacking on two or three levels with overlapping between dies by half (stacks , and ).Starting from the conclusions of previous analysis our approach for this thermal modeling relies on three essential considerations.3) Linear regime is considered; thus the principle of superposition can be applied and the temperature increase of devices can be estimated independently of reference case temperature; with these conditions the analytical approach is given following procedure.a) Self-heating of the active device in the " " level of the " " levels stacking structure is C C (2) b) The temperature increase in the " " level of the " " levels stacking structure is then given by the relationship  where is the cumulative thickness (expressed in m) of BCB layers under " " level at the position, is the number of BCB/Si interfaces under " " level at the position, the dissipated power density (expressed in W/cm ) in the " " level at the position.The corresponding results for this projection are reported in Table II.In this evaluation, we have considered three values of interfacial thermal conductance: supposing a perfect thermal transfer at each interface, W/m .K extracted by preliminary steady-state thermal characterization of thinned PTCB chip in single level UTCS test structure on wafer probe station, and W/m .K extracted by fitting a experimental transient response with 3-D simulation results.The part of thermal resistance relative to the heat transfer through successively the silicon host substrate, the Pb/Sn solder and the AlN header, estimated by 1-D approach, induces a temperature increase of about 0.6 C. Assuming 70 C case temperature, it appears that the hottest point will not be higher than 104 C in worst case, which makes the stacking structure compliant with space specifications, with the better packaging efficiency in terms of degree of integration.It is also important to observe for each level a maximum temperature increase practically equivalent to the one observed for other , and stacked devices.Indeed, for shifted stacking, the thermal coupling effects between the different levels are replaced by a self-heating mechanism through a most resistant thermal path (the cumulative layer thickness of the poor conductor BCB is higher).Finally, one can note a smaller temperature increase in the package which not exceed 5 C when the good thermal transfer at the interfaces is considered.

VI. CONCLUSIONS
The new ultrathin chip stacking technology has been evaluated on the point of view of the thermal performance.A 3-D FEM model was first used to confirm the expected heat flow distribution and transfer limitation by the BCB adhesive and planarization layers inserted between thinned active devices.A study of sensitivity to the size of the heating area has shown that devices dissipating a high power density have to be considered with caution.Indeed, for example, for a 10 10 m device transferred on 3 m of BCB adhesive layer, the apparent thermal resistance becomes 2.4 times higher than the one of the unthinned structure, in spite of a beneficial effect of the heat spreading in the high conductive thinned device.It is clear that with this stacking process the possible power systems will be located into the first level.
The first experimental characterizations by the thermal transient method have benefit from the accuracy provided by 3-D FEM calculations, essentially to well account for thermal decoupling between heating resistor and diode sensor in the used specific test chip.
For the objective of the design optimization of this new packaging technique, our true 3-D modeling approach, with a parameter sensitivity study, allowed to quantify the thermal transfer improvement brought by the embedding of copper grid or plate between the stacked thin chips.Heat extraction enhancement is advantageous 1) for the vertical heat transfer since the metal replaces a part of BCB; 2) for the temperature uniformization into the possible sticking defects areas thanks to its heat spreader capability; 3) by adding lateral conduction path at the peripheral zones of the stacked structure.The technological constraints, and probably the electrical added function (ground plane notably), will direct the choice of either solution by imposing some inevitable tradeoffs.
Finally, all conclusions of this presented modeling study are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application and currently under development.It is shown that the most compact stacking structure among the considered options remains compliant with spatial thermal specifications.

Thermal
Modeling and Management in Ultrathin Chip Stack Technology Stéphane Pinel, Antoine Marty, Josiane Tasselli, Jean-Pierre Bailbe, Eric Beyne, Rita Van Hoof, Santiago Marco, Joan Ramon Morante, Olivier Vendier, and Marc Huan Abstract-This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process.Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack.Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules.This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area.First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented.For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties.It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered.Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.Index Terms-Benzocyclobutene, copper, FEM, MCM, thermal simulation, thermal transient, thin dies, 3-D integration.

Fig. 1 .
Fig. 1.Schematic of the ultra thin chip stacking technology configuration.

Fig. 2 .
Fig. 2. Design rules of MCM-D technology considered in 3-D FEM thermal modeling.

Fig. 5 .
Fig. 5. Surface temperature contours of the PTCB single-level structure.Only one heat resistor is on and dissipates 1 W.
Authorized licensed use limited to: Universitat de Barcelona.Downloaded on February 16, 2009 at 04:17 from IEEE Xplore.Restrictions apply.

Fig. 8
gives a typical global response of the expected thermal impedance for this stacked structure: log-time representation shows clearly the separation of the sequential heat propagation times.The times range of interest in this transient analysis is limited to the small values (until 100 ms for the heat transfer trough thinned PTCB chip, BCB attach layer and Si host substrate).Therefore, our 3-D model (restricted to the half structure) considers for the higher time values a simplified modeling approach by effective thermal transfer through epoxy attach layer, Al O carrier and forced convection by backside only.The exchange area is 2.5 1.25 cm and the reference temperature is 18 C.A first fitting procedure with 3-D FEM simulation results, made in the first propagation time sequence by imposing a value of 0.2 W/m.K for thermal conductivity of

Fig. 8 .
Fig. 8. Experimental and simulated transient temperature responses for the PTCB test device mounted in single-level UTCS structure.

Fig. 9 .
Fig. 9. Schematic view of the simulated two-levels structure with embedded Cu grid or Cu plate thermal drains.

Fig. 10 .
Fig. 10.Three-dimensional views of the quarter of two stacked PTCB structures embedding a Cu grid.

Fig. 11 .
Fig. 11.Temperature distributions (a) onto the top of the second level and (b) onto the upper side of the Cu grid for heat on and equal to 0.5 W. Superposition of the heat and heat effects is observed in temperature distributions calculated on (c) the Ox symmetry axis for each level.

Fig. 12 .
Fig. 12.Comparison of heat extraction efficiencies for copper grid or full copper plate having same thickness (2 m).
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Fig. 13 .
Fig. 13.Evaluation of the effective transverse thermal transfer length by a FEM modeling of one specific small slice.

Fig. 14 .
Fig. 14.Increase of heat extraction capabilities of embedded drains when the transverse component of the thermal resistance decreases.

Fig. 15 .
Fig. 15.Evaluation of thermal extraction capabilities of Cu grid or Cu plate for the prevention of sticking defects through the study of void size influence.1)One-dimensional thermal conduction model is a good approximation for these large active devices with uniform dissipated power.2) Thermal effects relative to SiO layers and metallic interconnections in processed area of the thinned dies have been ignored; indeed, starting from W/m.K and W/m.K, 1 m of SiO layer has the same effect than 0.1 m of BCB and the very small size of interconnection lines minimizes the thermal transfer.
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TABLE I THERMAL
PROPERTIES OVERVIEW OF THE MATERIALS USED IN THE FEM SIMULATIONS

TABLE II COMPARISON
OF THERMAL BEHAVIOURS CALCULATED FOR THE DIFFERENT STACKING TOPOLOGIES OF THE THREE-LEVELS SPACE DEMONSTRATOR.DISSIPATED POWER IN EACH LEVEL IS 4 W (1.78 W/cm )