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dc.contributor.authorMauricio, Joan-
dc.contributor.authorFreixas, Lluis-
dc.contributor.authorSanuy Charles, Andreu-
dc.contributor.authorGomez, Sergio-
dc.contributor.authorManera, Rafel-
dc.contributor.authorMarin, Jesus-
dc.contributor.authorPerez, Jose M.-
dc.contributor.authorPicatoste Olloqui, Eduardo-
dc.contributor.authorRato, Pedro-
dc.contributor.authorSanchez, David-
dc.contributor.authorSanmukh, Anand-
dc.contributor.authorVela, Oscar-
dc.contributor.authorGascón Fora, David-
dc.description.abstractThis paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronics-
dc.format.extent16 p.-
dc.relation.isformatofReproducció del document publicat a:
dc.relation.ispartofElectronics, 2021, vol. 10, num. 15, p. 1-16-
dc.rightscc-by (c) Mauricio, Joan et al., 2021-
dc.sourceArticles publicats en revistes (Física Quàntica i Astrofísica)-
dc.subject.classificationDisseny de circuits electrònics-
dc.subject.classificationCircuits integrats-
dc.subject.otherElectronic circuit design-
dc.subject.otherIntegrated circuits-
dc.titleMATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution-
Appears in Collections:Articles publicats en revistes (Institut de Ciències del Cosmos (ICCUB))
Articles publicats en revistes (Física Quàntica i Astrofísica)

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