Please use this identifier to cite or link to this item: https://hdl.handle.net/2445/215181
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dc.contributor.advisorAtserias, Albert-
dc.contributor.authorCantero de Arriba, Carlos-
dc.date.accessioned2024-09-16T14:41:19Z-
dc.date.available2024-09-16T14:41:19Z-
dc.date.issued2024-09-
dc.identifier.urihttps://hdl.handle.net/2445/215181-
dc.descriptionTreballs Finals del Màster de Lògica Pura i Aplicada, Facultat de Filosofia, Universitat de Barcelona. Curs: 2024-2024. Tutor: Albert Atseriasca
dc.description.abstractThe aim of this work is to formalize the circuit-size lower bound showed by Kannan in 1982 in a weak theory for feasible computations. In particular, we will work with theories of bounded arithmetic, which are subtheories of Peano Arithmetic that weaken its induction axiom scheme by restricting it to formulas in which the quantifiers are bounded. Kannan’s circuit lower bound states that for every fixed polynomial size of circuits, there is a language in the second level of the polynomial hierarchy that cannot be decided by circuits of that size. We note that the essential ingredient in this proof is a key use of the weak pigeonhole principle, which is available in bounded arithmetic. Instrumental in the proof of Kannan’s Theorem is the celebrated Karp-Lipton’s Theorem, stating that if the satisfiability problem for propositional formulas can be decided by polynomial-size circuits then the polynomial hierarchy collapses to its second level, which we also formalize in the same theoryca
dc.format.extent68 p.-
dc.format.mimetypeapplication/pdf-
dc.language.isoengca
dc.rightscc by-nc-nd (c) Cantero, 2024-
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.sourceMàster Oficial - Pure and Applied Logic / Lògica Pura i aplicada-
dc.subject.classificationLògica matemática-
dc.subject.classificationComplexitat computacional-
dc.subject.classificationCircuits integrats-
dc.subject.classificationTreballs de fi de màster-
dc.subject.otherMathematical logic-
dc.subject.otherComputational complexity-
dc.subject.otherIntegrated circuits-
dc.subject.otherMaster's thesis-
dc.titleA Formalization of Kannan’s Circuit Lower Bound in Bounded Arithmeticca
dc.typeinfo:eu-repo/semantics/masterThesisca
dc.rights.accessRightsinfo:eu-repo/semantics/openAccessca
Appears in Collections:Màster Oficial - Pure and Applied Logic / Lògica Pura i aplicada

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