# name
Design of SiPM Front-End Readout Integrated Circuits for Large Area Single-Photon Imagers

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Universitat de Barcelona. Facultat de Física

# metadata.dc.description.abstract[].value
[eng] The demand for particle detectors with superior timing performance and precise energy measurement has significantly increased in recent years. Applications requiring extensive detection areas, such as Time-of-Flight Positron Emission Tomography (ToF-PET), particle detectors in high-energy physics experiments like the Large Hadron Collider beauty (LHCb) at CERN, and the advanced cameras for the Large-Size Telescope (LST) in the Cherenkov Telescope Array (CTA), pose significant challenges. These challenges include ensuring the scalability of electronics and maintaining reasonable power consumption. This thesis presents the design of various electronic integrated circuits tailored for these applications. Specifically, it details the design and implementation of the analog blocks within three different Application-Specific Integrated Circuits (ASICs).

A study on the optimization of timing resolution of readout electronics for SiPMs based on simulations is presented. The design of the most critical stages, particularly the Front-End (FE) input stage in current mode, is discussed. The performance of three different technologies (180, 130, and 65 nm) is evaluated, with 65 nm emerging as the best option for achieving good timing resolution with lower power consumption. Dividing the sensor into smaller segments improves the Single-Photon Electronic Jitter (SPEJ), but does not result in better Coincidence Time Resolution (CTR) when keeping the power per unit area constant, performing analog summation, or using an averaging algorithm of the timestamps for small LSO:Ce:0.2%Ca scintillator crystals.

The FastIC is an 8-channel analog FE ASIC developed in 65 nm CMOS technology, with a total area of 2×2 mm2. It can be used for the readout of positive and negative polarity photosensors with picosecond time resolution and intrinsic amplification. Thanks to its three-branch architecture, it provides a precise timestamp, a linear energy measurement, and triggering. Experimental measurements show an improvement over its predecessor, the HRFlexToT, in both time and energy resolution.

The FastRICH is a 16-channel ASIC, also developed in 65 nm CMOS technology, specifically designed for the Ring Imaging Cherenkov (RICH) detector of the LHCb experiment at CERN. It reads out sensors like PMTs for use at the LHC Run 4 and SiPM candidates for Run 5. Building on the experience with the FastIC ASIC, it adapts its architecture and adds specific features required for the RICH detector, such as a Constant Fraction Discriminator (CFD) and an integrated Time-to-Digital Converter (TDC). The positive polarity input stage is optimized for the readout of SiPMs with an area of 1×1 mm2 operating in a single-photon regime.

The Preamplifier Readout Electronics for the Summation of SiPMs Enhanced Circuit (PRESSEC) is a 16-input ASIC in development in 65 nm CMOS technology for the readout of SiPMs in the new camera update for the LST of the CTA. It will be capable of summing the signal in 4-input clusters and providing a mechanism to measure the Night Sky Background (NSB). The input stage is designed for large SiPMs (∼6×6 mm2) but can accommodate different sizes such as 3×3 mm2. It presents a dynamic range of 250 photoelectrons per cluster with a linearity error below 5% and a single-photon SNR greater than 5 in both charge and amplitude measurement.

# metadata.dc.description.abstract[].value
[cat] Aquesta tesi aborda la creixent demanda de detectors de partícules amb una resolució temporal superior i una mesura precisa de l’energia, crucial per a diverses aplicacions com la Tomografia per Emissió de Positrons amb Temps de Vol (ToF-PET), detectors de partícules en experiments de física d'altes energies com LHCb al CERN, i la càmera avançada per als Telescopis de Gran Mida (LST) a la Matriu de Telescopis Cherenkov (CTA). En particular, se centra en les aplicacions que requereixen àrees de detecció grans combinades amb alta precisió temporal al nivell d’un sol fotó. S’exploren els conceptes de segmentació de sensors i suma de senyals. Aquesta tesi presenta el disseny de circuits integrats electrònics adaptats a aquestes aplicacions, detallant els blocs analògics dins de tres ASICs. Inclou un estudi sobre l'optimització de la resolució temporal per a Fotomultiplicadors de Silici (SiPM), destacant la tecnologia de 65 nm com a òptima per a una bona resolució temporal amb un baix consum d'energia. L'ASIC FastIC proporciona una millor resolució temporal i energètica que el seu predecessor, mentre que l'ASIC FastRICH està adaptat als requisits específics del detector RICH en l'experiment LHCb. L'ASIC PRESSEC, en desenvolupament, té com a objectiu millorar la lectura de SiPM per a la nova actualització de la càmera per als LSTs, oferint capacitats per a la suma de senyals i la mesura del Fons del Cel Nocturn (NSB).

# metadata.dc.rights[].value
cc by-nc-nd (c) Manera Escalero, Rafel, 2024

# metadata.dc.title[].value
Design of SiPM Front-End Readout Integrated Circuits for Large Area Single-Photon Imagers