Mauricio, J.Gascón Fora, DavidCiaglia, D.Gómez, SFernández, G.Sanuy Charles, Andreu2018-01-262018-01-262016-12-191748-0221https://hdl.handle.net/2445/119321This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, < 4-ps time resolution, up to 10 MHz of sustained input rate per channel, 45 mW of power consumption and very low area (910×215 μm2) in a commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.11 p.application/pdfengcc-by (c) Mauricio, J. et al., 2016http://creativecommons.org/licenses/by/3.0/esDisseny de circuits electrònicsCircuits integrats a molt gran escalaElectronic circuit designLarge scale integration of circuitsinfo:eu-repo/semantics/article6664972018-01-26info:eu-repo/semantics/openAccess