Bafleur, MariseBuxo, JuanPuig i Vidal, ManuelGivelin, P.Macary, V.Sarrabayrouse, G.2009-06-192009-06-1919930018-9383https://hdl.handle.net/2445/8761The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.3 p.application/pdfeng(c) IEEE, 1993Circuits integratsCircuits electrònicsMOS integrated circuitsPower integrated circuitsSwitching circuitsApplication of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technologyinfo:eu-repo/semantics/article73504info:eu-repo/semantics/openAccess