Mauricio Ferré, JoanFreixas, LluisSanuy Charles, AndreuGómez, SergioManera Escalero, RafelMarin, JesusPerez, Jose M.Picatoste Olloqui, EduardoRato, PedroSánchez, DavidSanmukh, AnandVela, OscarGascón Fora, David2022-02-212022-02-212021-08-012079-9292https://hdl.handle.net/2445/183380This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronics16 p.application/pdfengcc-by (c) Mauricio, Joan et al., 2021https://creativecommons.org/licenses/by/4.0/Disseny de circuits electrònicsCircuits integratsElectronic circuit designIntegrated circuitsinfo:eu-repo/semantics/article7172912022-02-21info:eu-repo/semantics/openAccess