Vilà i Arbonès, Anna MariaMartí Farràs, Carles2021-10-052021-10-052021-02https://hdl.handle.net/2445/180383Treballs Finals de Grau de Física, Facultat de Física, Universitat de Barcelona, Curs: 2021, Tutora: Anna Maria Vilà ArbonèsSuccessive-approximation (SAR) analog-to-digital converters (ADCs) are among the most common and widely used general-purpose ADC architectures for their moderate resolutions and sampling rates. This paper aims to study and understand the conventional SAR ADC by proposing an N-bit architecture with a split capacitor digital-to-analog converter (DAC), and design, simulate, and finally implement a functional 8-bit 1-kS/s 0-5V SAR ADC prototype on a breadboard. The simulations and the tested prototype allow us to analyze the results and notice some of the most relevant advantages and disadvantages of the SAR ADC besides its limitations5 p.application/pdfengcc-by-nc-nd (c) Martí, 2021http://creativecommons.org/licenses/by-nc-nd/3.0/es/Convertidors analògic-digitalsSimulació per ordinadorTreballs de fi de grauAnalog-to-digital convertersComputer simulationBachelor's thesesinfo:eu-repo/semantics/bachelorThesisinfo:eu-repo/semantics/openAccess