Please use this identifier to cite or link to this item:
Title: Residual thermomechanical stresses in thinned-chip assemblies
Author: Leseduarte Cuevas, Sergio
Marco Colás, Santiago
Beyne, Eric
Van Hoof, Rita
Marty, Antoine
Pinel, Stèphane
Vendier, Olivier
Coello-Vera, Augustín
Keywords: Delamination
Finite element analysis
Integrated circuit design
Integrated circuit interconnections
Integrated circuit packaging
Thermal stresses
Circuits integrals
Issue Date: 2000
Publisher: IEEE
Abstract: A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 m. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method.
Note: Reproducció del document publicat a
It is part of: IEEE Transactions on Components Packaging and Manufacturing Technology Part A, 2000, vol. 23, núm. 4, p. 673-679.
Related resource:
ISSN: 1521-3331
Appears in Collections:Articles publicats en revistes (Enginyeria Electrònica i Biomèdica)

Files in This Item:
File Description SizeFormat 
154101.pdf326.56 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.