Please use this identifier to cite or link to this item: http://hdl.handle.net/2445/8724
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dc.contributor.authorPinel, Stèphanecat
dc.contributor.authorMarty, Antoinecat
dc.contributor.authorTasselli, Josianecat
dc.contributor.authorBailbe, Jean-Pierrecat
dc.contributor.authorBeyne, Ericcat
dc.contributor.authorVan Hoof, Ritacat
dc.contributor.authorMarco Colás, Santiagocat
dc.contributor.authorMorante i Lleonart, Joan Ramoncat
dc.contributor.authorVendier, Oliviercat
dc.contributor.authorHuan, Marccat
dc.date.accessioned2009-06-18T08:31:52Z-
dc.date.available2009-06-18T08:31:52Z-
dc.date.issued2002cat
dc.identifier.issn1521-3331cat
dc.identifier.urihttp://hdl.handle.net/2445/8724-
dc.description.abstractThis paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.eng
dc.format.extent10 p.cat
dc.format.mimetypeapplication/pdfeng
dc.language.isoengeng
dc.publisherIEEEcat
dc.relation.isformatofReproducció del document publicat a http://dx.doi.org/10.1109/TCAPT.2002.1010013cat
dc.relation.ispartofIEEE Transactions on Components Packaging and Technologies, 2002, vol. 25, núm. 2, p. 244-253.eng
dc.relation.urihttp://dx.doi.org/10.1109/TCAPT.2002.1010013-
dc.rights(c) IEEE, 2002cat
dc.subject.classificationAnàlisi tèrmicacat
dc.subject.classificationAdministraciócat
dc.subject.otherFinite element analysiseng
dc.subject.otherThermal conductivityeng
dc.subject.otherThermal management (packaging)eng
dc.titleThermal modeling and management in ultrathin chip stack technologycat
dc.typeinfo:eu-repo/semantics/articlecat
dc.typeinfo:eu-repo/semantics/publishedVersion-
dc.identifier.idgrec505014cat
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess-
Appears in Collections:Articles publicats en revistes (Electrònica)

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