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Please use this identifier to cite or link to this item: https://hdl.handle.net/2445/119321
Matrix: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure
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This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, < 4-ps time resolution, up to 10 MHz of sustained input rate per channel, 45 mW of power consumption and very low area (910×215 μm2) in a commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.
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MAURICIO, J., et al. Matrix: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure. Journal of Instrumentation. 2016. Vol. 11, num. 12, pags. 1-9. ISSN 1748-0221. [consulted: 9 of October of 2026]. Available at: https://hdl.handle.net/2445/119321