Fitxers
Tipus de document
ArticleVersió
Versió publicadaData de publicació
Tots els drets reservats
Si us plau utilitzeu sempre aquest identificador per citar o enllaçar aquest document: https://hdl.handle.net/2445/8692
Residual thermomechanical stresses in thinned-chip assemblies
Títol de la revista
Director/Tutor
ISSN de la revista
Títol del volum
Recurs relacionat
Resum
A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 m. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method.
Matèries (anglès)
Citació
Citació
LESEDUARTE CUEVAS, Sergio, et al. Residual thermomechanical stresses in thinned-chip assemblies. IEEE Transactions on Components Packaging and Manufacturing Technology Part A. 2000. Vol. 23, núm. 4, pàgs. 673-679. ISSN 1521-3331. [consulta: 12 de maig de 2026]. Disponible a: https://hdl.handle.net/2445/8692