Toward ML-Based State Discrimination on FPGA in Open-Source Quantum Control Electronics

Abstract

Low-latency and high-fidelity qubit state measurement is essential for superconducting quantum computing, particularly for enabling mid-circuit measurements and real-time feedback. While commercial control hardware increasingly supports onFPGA state discrimination, these platforms operate on closed firmware that precludes custom signal processing pipelines. Open-source FPGA frameworks offer an alternative path: full programmatic access to the readout chain, letting researchers integrate custom algorithms, including machine learning, directly into the measurement workflow. This thesis documents the setup and characterisation of a QICK-based [1] readoutsystem on a Xilinx ZCU216 RFSoC platform, covering FPGA configuration, DDS based waveform generation, and the analogue front-end signal path. The work establishes a functional loopback signal chain, validated end-to-end from pulse generation to demodulated IQ data, together with the calibration workflow needed to drive and read out superconducting resonators once a device is attached, and examines the constraints the hardware places on dispersive qubit readout at the target resonator frequencies. Using existing single-shot readout data from a superconducting qubit device, we design and evaluate a machine-learning-assisted state discrimination pipeline. On integrated IQ data, linear discriminant analysis is already near-optimal: none of the twenty MLP architectures we tested improves on it, as expected from the Gaussian structure of the IQ clouds. The only meaningful gain comes from a lightweight 1D CNN trained on synthetic raw ADC traces built from the real device's IQ statistics, which recovers shots corrupted by mid-readout T1 relaxation that integrated methods cannot distinguish. On a synthetic test set the CNN reaches 99.75% overall delity and 98.4% accuracy on relaxation shots, against 44.3% for LDA on the same 122 shots. This model is trained and evaluated entirely offine; real-time deployment within the QICK firmware was not achieved in this work. The thesis instead closes by outlining the path toward it: the data collection procedure required on the ZCU216, the model adaptation and quantisation constraints imposed by the programmable logic fabric, and the methodology needed to test whether deployment improves classi cation speed, fidelity, or both.