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Si us plau utilitzeu sempre aquest identificador per citar o enllaçar aquest document: https://hdl.handle.net/2445/183380
MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution
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This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronics
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MAURICIO FERRÉ, Joan, et al. MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution. Electronics. 2021. Vol. 10, num. 15, pags. 1-16. ISSN 2079-9292. [consulted: 13 of August of 2026]. Available at: https://hdl.handle.net/2445/183380