Please use this identifier to cite or link to this item: http://hdl.handle.net/2445/8724
Title: Thermal modeling and management in ultrathin chip stack technology
Author: Pinel, Stèphane
Marty, Antoine
Tasselli, Josiane
Bailbe, Jean-Pierre
Beyne, Eric
Van Hoof, Rita
Marco Colás, Santiago
Morante i Lleonart, Joan Ramon
Vendier, Olivier
Huan, Marc
Keywords: Anàlisi tèrmica
Administració
Finite element analysis
Thermal conductivity
Thermal management (packaging)
Issue Date: 2002
Publisher: IEEE
Abstract: This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.
Note: Reproducció del document publicat a http://dx.doi.org/10.1109/TCAPT.2002.1010013
It is part of: IEEE Transactions on Components Packaging and Technologies, 2002, vol. 25, núm. 2, p. 244-253.
URI: http://hdl.handle.net/2445/8724
ISSN: 1521-3331
Appears in Collections:Articles publicats en revistes (Electrònica)

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