Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

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dc.contributor.authorBafleur, Marise
dc.contributor.authorBuxo, Juan
dc.contributor.authorPuig i Vidal, Manuel
dc.contributor.authorGivelin, P.
dc.contributor.authorMacary, V.
dc.contributor.authorSarrabayrouse, G.
dc.date.accessioned2009-06-19T08:21:42Z
dc.date.available2009-06-19T08:21:42Z
dc.date.issued1993cat
dc.description.abstractThe aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.eng
dc.format.extent3 p.cat
dc.format.mimetypeapplication/pdfeng
dc.identifier.idgrec73504cat
dc.identifier.issn0018-9383
dc.identifier.urihttps://hdl.handle.net/2445/8761
dc.language.isoengeng
dc.publisherIEEEcat
dc.relation.isformatofReproducció del document publicat a http://dx.doi.org/10.1109/16.216442cat
dc.relation.ispartofIEEE Transactions on Electron Devices, 1993, vol. 40, núm. 7, p. 1340-1342.cat
dc.relation.urihttp://dx.doi.org/10.1109/16.216442
dc.rights(c) IEEE, 1993cat
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess
dc.sourceArticles publicats en revistes (Enginyeria Electrònica i Biomèdica)
dc.subject.classificationCircuits integratscat
dc.subject.classificationCircuits electrònicscat
dc.subject.otherMOS integrated circuitseng
dc.subject.otherPower integrated circuitseng
dc.subject.otherSwitching circuitseng
dc.titleApplication of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technologyeng
dc.typeinfo:eu-repo/semantics/articleeng
dc.typeinfo:eu-repo/semantics/publishedVersion

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