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Bachelor thesis

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cc-by-nc-nd (c) Martí, 2021
Please use this identifier to cite or link to this item: https://hdl.handle.net/2445/180383

Design and Implementation of an 8-Bit 1-kS/s Successive-Approximation ADC

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Abstract

Successive-approximation (SAR) analog-to-digital converters (ADCs) are among the most common and widely used general-purpose ADC architectures for their moderate resolutions and sampling rates. This paper aims to study and understand the conventional SAR ADC by proposing an N-bit architecture with a split capacitor digital-to-analog converter (DAC), and design, simulate, and finally implement a functional 8-bit 1-kS/s 0-5V SAR ADC prototype on a breadboard. The simulations and the tested prototype allow us to analyze the results and notice some of the most relevant advantages and disadvantages of the SAR ADC besides its limitations

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Treballs Finals de Grau de Física, Facultat de Física, Universitat de Barcelona, Curs: 2021, Tutora: Anna Maria Vilà Arbonès

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Citation

MARTÍ FARRÀS, Carles. Design and Implementation of an 8-Bit 1-kS/s Successive-Approximation ADC. [consulted: 13 of August of 2026]. Available at: https://hdl.handle.net/2445/180383

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