Design and Implementation of an 8-Bit 1-kS/s Successive-Approximation ADC

Abstract

Successive-approximation (SAR) analog-to-digital converters (ADCs) are among the most common and widely used general-purpose ADC architectures for their moderate resolutions and sampling rates. This paper aims to study and understand the conventional SAR ADC by proposing an N-bit architecture with a split capacitor digital-to-analog converter (DAC), and design, simulate, and finally implement a functional 8-bit 1-kS/s 0-5V SAR ADC prototype on a breadboard. The simulations and the tested prototype allow us to analyze the results and notice some of the most relevant advantages and disadvantages of the SAR ADC besides its limitations